1. Field of the Invention
The invention generally relates to digital signal processing and more particularly to a sample rate converter.
2. Description of the Related Art
As computer systems find increased applications in every day life, sample rate conversion is becoming necessary in more situations. In general, a sample rate converter (SRC) converts a digital signal having a first sample rate to a substantially similar digital signal having a second sample rate. This allows two digital processing systems operating at two different sample frequencies/rates to transfer and process each other's signals. In the audio industry, applications of an SRC are numerous given that no standard sample rate has been adopted for all applications. For example, while a sample rate of 48 kHz is generally used in compact disc (CD) recording, 44.1 kHz is used for CD playback. Similarly, while digital audio tape (DAT) generally has a sample rate of 48 kHz, motion-picture-expert-group (MPEG) and Dolby AC-3 may have sample rates of 48 kHz, 44.1 kHz, 32 kHz, or half of any of these rates. Even if two separate systems have the same nominal sampling rate, they may not share the same master clock, in which case sample rate conversion is still required.
There are three well-known methods of sample rate conversions: digital-analog-digital (DAD), synchronous, and asynchronous. The most direct method of sample rate conversion is DAD. Under the DAD method, a digital-to-analog (D/A) converter converts an input digital signal into an analog signal. The analog signal, which consists of infinitely many repetitions of a frequency spectrum centered on multiples of the sampling rate is then sent to a lowpass filter to filter out the repetitions of the frequency spectrum and leave only the baseband frequency spectrum. An analog-to-digital (A/D) converter is next used in resampling the analog signal from the A/D converter at sample rate F.sub.s2 to convert the analog signal back into a digital signal. If F.sub.s2 is greater than 2* (F.sub.s1 /2), Shannon's sampling theorem is met and the original signal can be reconstructed completely from the sampled signal D. The drawback of the DAD method is that it does not operate in the robust digital domain and is therefore susceptible to all the sources of error that A/D and D/A converters are susceptible to such as temperature, supply voltage, and semiconductor wafer process variations.
For the synchronous sample rate conversion method, as its name suggests, the input and output sample rates originate from a master source. In other words, the input sample rate is related to the output sample rate by a ratio of integers (e.g., 3:2). In synchronous sample rate conversion, an input digital signal, which has a sample rate F.sub.s1 is provided as input to an interpolator. The interpolator interpolates the input digital signal by an integer factor U to increase the sample rate to that of the least common multiple (LCM) rate of the two sample rates, F.sub.s1 and F.sub.s2. Generally, in an interpolation operation, samples of value zero are inserted at sample times between the samples of the input signal. Since samples are added while the time span remains the same, the interpolated signal has a higher sampling rate than the input signal. The interpolated signal is next provided as input to a lowpass filter to eliminate unwanted periodic repetitions of the frequency spectrum between the frequency range 0&lt;f&lt;2.pi.. The lowpass filter outputs a filtered signal to a decimator which downsamples the filtered signal by an integer factor D and scales the spectral replicas at 0 and 2.pi. to produce a signal having a sample rate of 2/3 F.sub.s1. Accordingly, the integer factor D has a value of two (2) in this example. This method of conversion only applies to the case where the input sample rate and the output sample rate come from a master clock source.
Asynchronous sample rate conversion can convert between any two input and output sample rates. In other words, for asynchronous sample rate conversion, the ratio of the input sample rate and the output sample rate may be irrational or the ratio of the input sample rate and the output sample rate may be rational but the LCM rate is too high for synchronous sample rate conversion to be practical. In a typical Prior Art asynchronous sample rate converter such as that described in a publication titled "Theory and VLSI Architectures for Asynchronous Sample Rate Converters," Robert Adams and Tom Kwan, 94th Convention of the Audio Engineering Society, Berlin, Germany, 1993, an input digital signal is first conceptually oversampled/interpolated to a very high sample rate UF.sub.s1. Next, this high sample rate signal UF.sub.s1 is filtered by a convolution low-pass filter before being resampled at another high rate DF.sub.s2. The high rate signal is then downsampled by a factor of D to produce the output signal.
For a classic convolution lowpass filter, such as that described in the background section of U.S. Pat. No. 5,335,194 entitled "Sample Rate Converter" by Clayton et al. herein incorporated by reference, with a cutoff of 20 kHz operating at a sample rate F.sub.s1 of 88.2 kHz to achieve approximately 110 dB the number of taps k required is 128. Equivalently, the number of taps k required for a sample rate F.sub.s1 of 44.1 kHz is 64. As a general rule, the number of taps in a filter is directly proportional to the accuracy of the approximated response. Since the oversample ratio U is 2.sup.16 (65,536), the total number of taps required for upsample rate UF.sub.s1 (where F.sub.s1 is 44.1 kHz) is 2.sup.16 * 64. As such, the amount of hardware required for the number of taps and their corresponding multiplication coefficients makes implementing a convolution lowpass filter an extremely difficult task under the classic convolution design. Under the Prior Art, however, the number of taps and their corresponding coefficients are reduced to manageable levels by recognizing that only one of every D samples need be computed, since the spectrum is eventually resampled at F.sub.s2. The number of taps k, used at any one time, is equal to the total number of taps divided by the upsampling ratio U (assuming for now U=D=2.sup.16). For the example given above, the number of non-zero samples is 64 which is very manageable. Accordingly, the number of taps required for computation of each output sample is 64.
However, all 2.sup.16 *64 coefficients still have to be stored even if only 64 of them are in use at any one time. Hence, a very large read-only-memory (ROM) is required for the above short cut. Moreover, in the short cut discussed above, the resampling introduces some aliased images into its output signal. Since no actual decimation filtering is being done, the aliased images cannot be filtered out and are somewhat magnified subsequently after downsampling. As a result, even more of a burden is put on the interpolation filter which leads to a bigger ROM and more computation.
Thus, a need exists for an apparatus, system, and method to perform sample rate conversion in an improved and economical fashion.